The present invention relates to semiconductor devices and, more particularly, the present invention relates to a technology that can be usefully applied to a semiconductor device having plural semiconductor chips on a wiring substrate.
Japanese Unexamined Patent Application Publication No. 2012-54597 discloses the configuration of a semiconductor device including: a package substrate on which semiconductor elements are mounted; a lid having a concave portion in which the semiconductor elements are housed and flanges formed around the outer peripheries of this concave portion; an adhesion layer formed between the semiconductor elements and the concave portion of the lid; and an adhesion layer formed between the package substrate and the flanges of the lid.
Further, Japanese Unexamined Patent Application Publication No. Hei07(1995)-50360 discloses the configuration of a semiconductor device including: a metal layer that is formed along the periphery of a surface arranged opposite to the body of a package as a ground for a solder layer and the width of which is made narrow or wide partly or here and there; and a lid substrate (lid).
Further, Japanese Unexamined Patent Application Publication No. Hei08(1996)-51167 discloses the configuration of a semiconductor device including a semiconductor package sealing lid for sealing semiconductor chips mounted on the semiconductor chip mounting section of a semiconductor package base substrate.